Rtl Verification

7 days ago


Ho Chi Minh City, Vietnam Sperton Global AS Full time

**Responsibilities**:

- Subsystem Integration (PCIe, DDR, USB)
- Integrate controller and PHY at RTL level.
- Integrate controller and PHY IP level SDC and generate subsystem level SDC.
- Pass subsystem simulation.
- Pass RTL QA items such as CDC, Lint, SDC validation.
- Perform Synthesis (RTL to Netlist)
- Pass QA items such as LEC, STA, and In-house Design Kit
- Generate HDM model (subsystem CDC model, for SOC level CDC)
- Generate subsystem document & database package.

**Requirements**:

- Familiar with System Verilog
- Familiar with Front-end EDA tools
- Logic simulation tool, Cadence Xcelium or Synopsys VCS
- Synopsys Design Compiler, PrimeTime, Lint
- LEC tool, Cadence Conformal or Synopsys Formality
- Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
- Familiar with PCIe Gen-4 spec
- Familiar with AMBA AXI, AHB, APB spec
- BS or MS degree in EE or CS related
- Good English communication skills
- Experience in UVM is a plus



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