Design Verification Engineer/senior
3 weeks ago
International company
- Full flow IC Design
- New project in Vietnam
Main Responsibilities
- IP/SOC design verification
- Building the RTL design verification team starting from finding well-qualified semiconductor
verification engineers
- Review the IP/SOC specification and architecture
- Extract the features and define the verification plan
- Execute on the verification plan through testbench development, test generation, failure analysis,
and coverage analysis/closure.
- RTL and gate level simulation
- Design verification methodology and flow implementation and improvement
Career Qualifications
- 6 to 8 years of experience in related work (SOC design verification)
- Good understanding of computer architecture and Verilog
- Understanding SOC design flow and methodology
- Capability to extract the design features and define the verification plan - Failure analysis and decision making
- Project schedule management
Preferred Qualifications
- Domain knowledge for CPU, coherent/noncoherent cache system, SOC bus, DRAM controller,
accelerators (NPU, GPU, DSP), multimedia and display IP (ISP, video codec, HDMI/DP)
- Working experience of UPF-based power-aware simulation, System Verilog Assertion (SVA),
scripts in languages such as Perl and/or Python
- Advanced knowledge of standard SoC design and verification flows including RTL design,
simulation and testbench development, coverage analysis and constrained random testing
586231
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