Principal Design Verification Engineer
2 months ago
Synopsys Solution Group is expanding our sub-system R&D team in Ho Chi Minh city, Vietnam. We’re seeking a highly motivated design verification engineer to join our growing highspeed interface sub-system R&D team.
Does this sound like a good role for you?
In this role, you will be responsible for:
- Defining verification plans and build verification environments for block/sub-system level designs using System Verilog with UVM.
- Write test cases, checkers, and coverage that implement the verification test plan.
- Work closely with RTL designers and other parts of our global verification team to debug failures.
**Key Qualifications**:
- Bachelor or Master degree in EE or CS, with 7 years’ experience in digital verification experience in the industry.
- Experience of verification of interfaces and controllers of one or more high-speed interface protocols such as PCI-Express, CXL, UCIe, HBM, DDR.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Experience of RTL verification using coverage driven verification techniques.
- Programming skill in C/Perl/Python.
- Proficient in HDL languages System Verilog, Verilog, or VHDL
- Good analytical, oral, and written communication skills.
- Self-motivated, proactive team player.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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