SOC Design Verification Senior Engineer
6 months ago
Semiconductor industry
- SoC Design Verification Senior Engineer
- Attractive salary package and benefit
**Main Responsibilities**
- IP/SOC design verification
- Review the IP/SOC specification and architecture
- Design verification methodology and flow implementation and improvement.
- Extract the features and define the verification plan
- Execute on the verification plan through testbench development, test generation, failure analysis, and coverage analysis/closure.
- Cooperate with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality.
- Supporting other RTL verification, integration and prototyping teams
- Support HW/SW Bring-up and debug
- RTL and gate level simulation
**Career Qualifications**
- 5+ years of experience in related work (SOC/IP design verification)
- Good understanding of computer architecture and Verilog
- Understanding SOC design flow and methodology.
- Capability to extract the design features and define the verification plan
- Failure analysis and decision making
- Basic knowledge of SystemVerilog and UVM
- Experience developing UVM based IP test-benches
- Project schedule management
**Preferred Qualifications**
- Domain knowledge for CPU, coherent/noncoherent cache system, SOC bus, DRAM controller, accelerators (NPU, GPU, DSP), multimedia and display IP (ISP, video codec, HDMI/DP)
- Working experience of UPF-based power-aware simulation, System Verilog Assertion (SVA).
- Advanced knowledge of standard SoC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing.
- Excellent knowledge of one of the scripting languages: Python, Perl, TCL, Csh.
- Proven knowledge of formal verification methodology
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