3.rtl Design
6 months ago
**Responsibilities**
- IP test-chip integration design and verification (memory IP and standard library IP)
- IP test chip development in advanced nodes Coordinate cross-site & cross-division communication & discussion
**Requirements**:
- At least 2 year experience in RTL design and verification
- Familiar with digital design flow & tools: Verilog, VCS, Verdi, Xcelium, UPF
- Scripting skills: Bash/C-shell, Perl, TCL, Python
- Familiar with Synopsys design compiler flow
- Familiar with Primetime STA flow
- Basic knowledge on Cadence Innovus and layout EDA tools is a plus
- Basic knowledge on physical verification (DRC/LVS) is a plus
- Chip tape-out experience is a plus
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Rtl Design Senior Engineer
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Rtl Designer
2 months ago
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Rtl Design Engineer
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4. SOC Rtl System Integration Senior Manager
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2.rtl System Integration Engineer
6 months ago
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Sr Staff Digital Engineer
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Sr Staff Rtl Design Engineer
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