Rtl Design Senior Engineer
7 months ago
Semiconductor industry
- RTL Design
- Attractive salary package and benefit
**Tasks of RTL/logic designer**
- Make design documents, integration guidelines.
- Write RTL code (Verilog, or System Verilog).
- Make IP configuration and generate RTL if the IP is provided from other vendors.
- Integrate IP into block, then release RTL of whole block including abstraction of block in IP-XACT format to build SOC.
- Cooperate with verification team to qualify the design.
**Main required skills**
- Mandatory skillsets are as below:
- Familiar with RTL/logic design flow, and the basic knowledge such as FSM, combinational logic, sequential logic, FIFO, etc.
- Understand well Verilog/System Verilog for synthesis
- Understand the design technics such as multi clock domain crossing (CDC), low power, etc.
- Understanding of SOC design flow and methodology
- Understand ARM bus protocols such as APB, AXI, ACE, etc.
- Understand peripheral protocols such as UART, SPI, I2C, etc.
- Understand sanity check (Lint check, CDC check, formal verification, and basic simulation)
- Support the physical implementation such as SDC constraint, DFT insertion, etc.
- Good understanding of CPU architecture, high-speed peripherals such as PCIe, DDRAM, MIPI CSI, ISP, Video standards, etc. is a plus.
- Basic knowledge about functional safety for automotive SOC is also a plus.
**Career Qualifications**
- Junior: 3+ years of experience in IP design or integration.
- Senior and above: 5+ years of experience in IP design or integration.
**Other skills**
- Task schedule management
- Self-investigation
- Reporting and problem explanation
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