2.rtl System Integration Engineer
6 months ago
**Responsibilities**
- Subsystem integration (PCIe, DDR, USB)
- Integrate controller and PHY at RTL level
- Integrate controller and PHY IP level SDC and generate subsystem level SDC
- Pass subsystem simulation
- Pass RTL QA items, such as CDC, Lint, and SDC validation
- Perform Synthesis (RTL to Netlist)
- Pass QA items, such as LEC, STA and in-house design kit
- Generate HDM model (subsystem CDC model, for SoC level CDC)
- Generate subsystem document & database package
**Requirements**:
- Familiar with system verilog
- Familiar with front-end EDA tools
- Logic simulation tool, Cadence Xcelium or Synopsys VCS
- Synopsys design compiler, PrimeTime, Lint
- LEC tool, Cadence Conformal or Synopsys Formality
- Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
- Familiar with PCIe Gen-4 spec
- Familiar with AMBA AXI, AHB, APB spec
- BS or MS degree in EE or CS related
- Good English communication skills
- Experience in UVM is a plus
- At least 2 year working experience
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