Rtl Design Manager

2 weeks ago


Ho Chi Minh City, Ho Chi Minh, Vietnam Adecco Full time

Job summary:

Job level:
Manager

Direct report:
Centre Head

Location:
HCM or Da Nang

Responsibilities:

Key Responsibilities

  • Implement design/testbench in System Verilog
  • Integrate IP blocks into larger SoC environment.
  • Design blocklevel microarchitectures
  • Support the entire chip life from design/implement/verification/bring up/validation.
  • Build, manage and guide a team of passionate engineers.

Experience requirements:

Qualifications

  • Handson 8+ years of experience in RTL development using Verilog/System Verilog.
  • Experience in microarchitecture development
  • Experience with onchip bus protocols (AXI, AXI-Lite etc.)
  • Experience with simulation tools like VCS/Verdi/Questa
  • Experience in multiclockdomain designs
  • Ability to work independently and good interpersonal skills

Education requirements:

  • Bachelor's and/or master's degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science.

Contact Person:

Toan Chu

Adecco

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