Rtl Design and Design Verification

1 week ago


Ho Chi Minh City, Ho Chi Minh, Vietnam NodeFlair Full time
Main Responsibilities (RTL Design)

  • Make design documents, integration guidelines.
  • Write RTL code (Verilog or SystemVerilog)
  • Make IP configuration and generate RTL if the IP is provided from other vendors.
  • Integrate IP into block, then release RTL of whole block including abstraction of block in IP-XACT format to build SoC.
  • Cooperate with Verification Team to qualify the design.
Required Skills (RTL Design)

  • Familiar with RTL/logic design flow and basic knowledge such as FSM, combinational logic, sequential logic, FIFO, etc.
  • Good understanding of Verilog/SystemVerilog for synthesis
  • Good understanding of design techniques such as multi clock domain crossing (CDC), low power, etc.
Career Qualifications (RTL Design)

  • Junior: 3+ years of experience in IP design or integration
  • Senior and above: 5+ years of experience in IP design or integration
Preferred Qualifications (RTL Design)

  • Task schedule management
  • Selfinvestigation
  • Reporting and problem explanation skills
Main Responsibilities (Design Verification)

  • IP/SoC design verification
  • Review the IP/SoC specification and architecture.
  • Design verification methodolgy and flow implementation and improvement
  • Extract the features and define the verification plan.
  • Execute on the verification plan through testbench development, test generation, failure analysis and coverage analysis/closure.
  • Cooperate with system engineers, HW/SW developors and other relevant functions to solve technical issues for quality.
  • Support other RTL verification, integration and prototyping teams.
  • Support HW/SW Bringup and debugging.
  • RTL and gatelevel simulation
Career Qualifications (Design Verification)

  • From 3 + to 5+ years of experience in related work (SoC/IP design verification)
  • Good understanding of computer architecture and Verilog
  • Understanding of SoC design flow and methodology
  • Capability to extract the design features and define the verification plan.
  • Failure analysis and decisionmaking skills
  • Basic knowledge of SystemVerilog and UVM
  • Experience developing UVMbased IP testbenches.
  • Project schedule management experience
Preferred Qualifications (Design Verification)

  • Domain knowledge for CPU, coherent/noncoherent cache system, SOC bus, DRAM controller, accelerators (NPU, GPU, DSP), multimedia and display IP (ISP, video codec, HDMI/DP)
  • Working experience of UPFbased poweraware simulation, System Verilog Assertion (SVA)
  • Advanced knowledge of standard SoC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing.
  • Excellent knowledge of one of the following scripting languages: Perl, TCL, Csh or Python
  • Proven knowledge of formal verification methodology
Preferred Character (for RTL Design & Design Verification)

  • Encouraging team members to be motivated with good coaching skills to accomplish their work
  • Good at 1:1 communication with team members to build up good relationship and work as a team
  • Facilitating collaboration within and across teams to address rootcause and debug issues.
  • Good decisionmaking skills and respectful of team members' opinions
  • Good communication skills to collaborate across teams and functions.


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