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4. SOC Rtl System Integration Senior Manager
3 months ago
Responsibilities
- SoC Integration (IP connectivity, IP configuration, Bus protocol design and etc.)
- Subsystem Integration (PCIe, DDR, USB and etc.)
- Integrate controller and PHY at RTL level
- Integrate controller and PHY IP level SDC, and generate subsystem level SDC
- Pass SoC, subsystem simulation
- Pass RTL QA items, such as CDC, Lint, and SDC validation
- Perform synthesis (RTL to Netlist)
- Pass QA items, such as LEC, STA, and inhouse design kit
- Generate HDM model (subsystem CDC model, for SoC level CDC)
- Generate subsystem document & database package
- Manage projects and update weekly progress to customers
Requirements:
- Familiar with System Verilog
- Familiar with Frontend EDA tools
- Logic simulation tool, Cadence Xcelium or Synopsys VCS
- Synopsys Design Compiler, PrimeTime, Lint
- LEC tool, Cadence Conformal or Synopsys Formality
- Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
- Familiar with PCIe Gen4 spec.
- Familiar with AMBA AXI, AHB, APB spec.
- Experience in ARM CPU, PCIe or USB 3.x system verification is a plus
- BS or MS degree in EE or CS related
- Good English communication skills
- Experience in UVM is a plus
- At least 12 year working experience