Junior/ Senior Memory Circuit Design Engineer
1 day ago
**1. Description**
Design, Optimization and Verification of IP Memory Compiler
Design include High-speed, High-density or Low-Power variant
Actively participate in design methodology and QA system improvement
Cooperate with Layout and CAD engineers for optimal schedule
Assist test-chip team in silicon verification and provide silicon validation report
Provide mentorship and guidance to junior
Familiar with DFT related flow and utilities is a plus
**2. Requirement**
Solid knowledge on SRAM architecture and design methodology
Solid knowledge on device physics, process variation and SRAM bit cell behavior
Familiar with Performance, Power and Area (PPA) design optimization
Familiar with Timing/Power characterization, Function Verification and other SRAM compiler QA tools setup
BS or MS degree in EE or CS related
Good English communication skills
Experience in Fin FET is a plus
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