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12. Senior Memory Layout Design Engineer
7 days ago
**Responsibilities**
- Study and perform physical verification deck QA
- Co-operate with circuit/layout team to define layout and QA methodologies for enhancing effectiveness and design quality
- Perform physical verification (LVS/DRC/ERC/EMIR)
- Ensure the database fully compliant with all requirements of tape-out flow
- Work with other engineers to achieve full chip integration, physical implementation, tape out and test-chip validation
- Work with IC design engineers to implement top quality layout for optimized block level design
**Requirements**:
- At least 3 year experience in layout memory IP design
- Self-motivate, efficient professional to work independently or in team
- Experience in memory layout, such as SRAM/ROM/TCAM
- Experience in the memory layout structure, sense amplifier, low power design, and power management
- Experience in floor-planning techniques, power mesh palling, signal routing, and matching layout
- Experience in FinFET layout techniques is a plus
- Able to estimate the schedule for the assignment layout
- Proficient in Cadence/Synopsys layout editor and physical verification tools
- Good English communication skills
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2 weeks ago
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