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Functional Verification Engineer
2 months ago
**Responsibilities**:
- Create and define verification plans;
- Develop verification environments for our ICs using Universal Verification Methodology (UVM);
- Draw on test scenarios using SystemVerilog;
- Verify functionality using the Constrained Random approach;
- Develop assertions in SystemVerilog for formal verification;
- Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies;
- Provide proactive support to users of our verification flow environment;
- Be responsible for our verification methods;
**Experience requirements**:
- Have at least 3 years of experience in Metric Driven Verification (digital and/or mixed-signal);
- Have capabilities and expertise in working with microcontroller-based ICs, as well as security and safety requirements;
- Have excellent know-how with UVM especially using SystemVerilog;
- Have knowledge of firmware and RTL design (VHDL);
- Ideally have knowledge of Cadence verification software;
**Education requirements**:
- A Bachelor’s degree in Electrical Engineering, Computer Science, or a similar academic discipline
**Contact Person**:
Thuy Trang Pham
Adecco
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