Senior Design Verification Engineers
7 months ago
**Mô tả công việc**:
(Mức lương: Thỏa thuận)
- Develop and implement verification plans to ensure the functional correctness of VLSI designs before they are fabricated.
- Create and maintain verification environments using advanced verification methodologies such as UVM (Universal Verification Methodology), OVM (Open Verification Methodology), or VMM (Verification Methodology Manual).
- Write and debug test cases, manage regression test suites, and analyze coverage reports to ensure comprehensive testing of VLSI designs.
- Collaborate with design engineers to identify and resolve design issues detected during the verification process.
- Enhance existing verification tools and processes to improve efficiency and effectiveness of the verification workflow.
- Mentor junior verification engineers and lead verification teams to achieve project goals within designated timelines.
- Stay updated with the latest trends and developments in VLSI verification methodologies and technologies.
Essential Skills
- In-depth knowledge of digital circuit design and verification.
- Expertise in SystemVerilog and any of the major verification methodologies like UVM, OVM, or VMM.
- Ability to develop verification plans that align with project scope and design complexity.
- Strong debugging skills and familiarity with simulation tools such as Cadence Xcelium, Mentor Questa, or Synopsys VCS.
Desirable Skills
- Experience with formal verification tools and methodologies.
- Knowledge of ASIC or FPGA design flow.
- Familiarity with advanced verification features such as assertions and functional coverage.
- Leadership skills with experience managing small teams or leading verification projects.
**Chức vụ**: Nhân Viên/Chuyên Viên
**Hình thức làm việc**: Toàn thời gian
**Quyền lợi được hưởng**:
- Competitive salary and benefits package including bonuses, health insurance, and retirement plans.
- Opportunities for professional growth and advancement within the company.
- Access to the latest tools and technologies in the field of VLSI design verification.
- Supportive work environment that encourages innovation and continuous learning.
- Flexibility in work hours and the possibility of remote work arrangements, depending on project requirements.
**Yêu cầu bằng cấp (tối thiểu)**: Trung cấp - Nghề
**Yêu cầu công việc**:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 5 years of experience in VLSI design verification.
- Proficient in SystemVerilog and at least one verification methodology (UVM, OVM, VMM).
- Strong analytical and problem-solving skills, with a proven track record of finding and fixing design flaws.
- Excellent communication skills, both verbal and written, with the ability to work effectively in a team environment.
- Experience with scripting languages such as Python, Perl, or Tcl is highly desirable.
**Yêu cầu giới tính**: Nam/Nữ
**Ngành nghề**: CNTT - Phần Mềm,Python
Trung cấp - Nghề
Không yêu cầu
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