SOC Frontend Implementation Engineer

2 weeks ago

Hanoi, Vietnam ADI Consulting Full time

Working Time Mon ~ Fri | Flexible coming time (7:00 - 10:00am)

Salary Negotiable

Rank Senior

Group Design Service

Department Design Centre

Perform all frontend implementation related works including but not limited to: netlist

synthesis, DFT implementation &Test vector generation, formal verification, and static

timing analysis.
- Develop and verify timing constraints based on the design specification; and

build the synthesis environment to synthesize digital, mix-signal chips in advanced

process nodes.
- Derive timing signoff factors to check the design timing with MCMM (multi

corners multi modes).
- Work with RTL design engineers to perform STA at a large million gates

design; to detect mismatch issues in RTL, build the constraint, optimize the circuit,

and analyze timing; to optimize and determine the critical paths; and to provide

the suggestion to RTL design engineers.
- Support to RTL design engineers in running Formality on ECO netlist; debug

mismatched errors of the ECO netlist; and debug timing violations.
- Work with layout engineers to isolate and identify the worst placement; to

choose an optimized cell layout structure; and support the timing report, ECO

fixing.
- Support DFT engineers to implement DFT test flow including scan insertion,

MBIST, scan compress/decompress for pin limited design, etc.
- Develop working methodologies which includes RTL synthesis flow, DFT

insertion flow and low power synthesis flow by using industry standard EDA tools.
- Use ASICs CAD support for multi-VDD designs and make use the benefits of

the power-intent designs using UPF.
- Support project managers with effort estimations and resource planning.
- Support team leader in coaching, training and development team members.

**Job Requirement**
- Education Required: University and above (Major: Electrical and Electronics,

Computer science)
- At least 5 years of experience in RTL synthesis, STA, DFT, Power Analysis

etc.
- Experience in multiple clocks designs and low power design such as: Dynamic

power optimization, MultiVt optimization, Clock gating, Dynamic and

Adaptive Voltage Frequency Scaling.
- Excellent in manipulate primetime TCL script to generate timing report for a

large design.
- Deep knowledge of: synthesis, timing, equivalent checks, RC-extraction, noise,

power, UPF, etc.
- Experienced in using EDA tools such as: Design Compiler, Power Compiler,

Formality, Primetime, Design For Test, TetraMax, etc.
- Good knowledge in Design For Test implementation.
- Good communication and interpersonal skills.
- Good at English
- Logical thinking
- Analytic and troubleshoot problem
- Careful
- Ability to multi-task and can work under deadline pressure.

**Benefits**
- Attractive salary with a 13-month salary bonus, lunch allowance, children

maintenance support, etc.
- Opportunities to join many big projects, overseas trips, career advancement,

etc.
- Social insurance based on full salary, periodic health check
- 14++ days leave. Monthly leave for female employees
- Company culture activities: company trips, monthly/quarterly events, etc.
- Flexible working hours.

**Job Types**: Full-time, Permanent

**Salary**: From 40,000,000₫ per month

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