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SOC Backend Implementation Engineer

4 weeks ago

Hanoi, Vietnam ADI Consulting Full time

Working Time Mon ~ Fri | Flexible coming time (7:00 - 10:00am)

Salary Negotiable

Rank Senior

Group Design Service

Department Design Centre

Responsible for all aspects of the SoC physical design flow including but not limited

to: floor-planning, place and route, timing and power, physical verification, and full

chip design database ready for manufacturing.
- Work with the FE team to understand chip architecture and dependencies

between different domains then drive physical aspects early in design cycle.
- Responsible for full chip physical design both flat and hierarchical.
- Create full chip floor plan including pin placement, partitions and power grid.
- Develop and validate high performance low power clock network guidelines.
- Perform block level place, route and close the design to meet timing, area and

power constraints.
- Generate and implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at chip/block level and come up with

guidelines and checklist, execute and track progress.
- Work with expert team to identify potential solution, drive execution and

improvement in PD work methodologies.
- Manage, assist, and resolve technical issues related to PD work with team

members.
- Work with counterparts in other sites to jointly execute projects as an integral

part of the team in global environment.
- Support project managers with effort estimations and resource planning.
- Support team leader in coaching, training and development team members.

**Job Requirement**
- Education Required: University and above (Major: Electrical and Electronics,

Computer science)
- At least 5 years of experience in Physical Design
- Experience in low power/multi voltage design and understanding of UPF.
- Worked on multiple tape-outs at ultra-deep sub-micron technologies, 28nm and

smaller nodes, in complex multi-million gate designs.
- Deep knowledge of Synopsys or Cadence implementation tools and flow.
- Have hands on experience in completing RTL to GDSII flow, which includes

synthesis, DFT, IO planning, floor-planning, power analysis, P&R, CTS,

extraction, timing closure, physical verification, rail analysis etc.,
- Strong technical knowledge in microelectronics and/or system architectures.
- Knowledge on package design, ESD, integration of analog and mixed signal

macros.
- Excellent debugging skills for design issues.
- Experience in using Perl and TCL/TK to achieve highly automated,

reproducible and fast results.
- Good communication and interpersonal skills.
- Good at English
- Logical thinking

**Benefits**
- Attractive salary with a 13-month salary bonus, lunch allowance, children

maintenance support, etc.
- Opportunities to join many big projects, overseas trips, career advancement,

etc.
- Social insurance based on full salary, periodic health check
- 14++ days leave. Monthly leave for female employees
- Company culture activities: company trips, monthly/quarterly events, etc.
- Flexible working hours.

**Job Types**: Full-time, Permanent

**Salary**: From 50,000,000₫ per month

Ability to commute/relocate:

- Hà Nội: Reliably commute or planning to relocate before starting work (required)