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Verification Engineer #
3 weeks ago
KEY SKILLS
Verification IPs
RTL Design
SystemVerilog
SV-UVM
OVM
Verification Engineer
Experience in **RTL** Functional Verification using **SystemVerilog, SV-UVM, OVM**.
Experience in Developing **Verification IPs**.
Experience in writing **Synthesizable Testbench and preformed Emulation**.
Experience in coding using **C, C++, Python, TCL, Perl, etc**.
Experience in Video, Networking, and LTE/5G Domains is an added advantage.
Experience in SoC verification from test planning till tape-out is added advantage.
Good Knowledge of various protocols and bus standards like **PCI, PCIe, Ethernet, USB, DDR-SDRAM, IIC, SPI, AXI, Avalon**,
Exp**:3-6 yrs**
Social health and unemployment insurance benefits will be provided
Glit
**Job Types**: Full-time, Permanent
**Salary**: 12,500₫ - 13,000₫ per month
COVID-19 considerations:
Always
Application Question(s):
- with Experience in RTL Functional Verification using SystemVerilog, SV-UVM, OVM?
- with Experience in Developing Verification IPs?
- with Experience in writing Synthesizable Testbench and preformed Emulation?
- with Experience in coding using C, C++, Python, TCL, Perl?
- with Good Knowledge of various protocols and bus standards like PCI, PCIe, Ethernet, USB, DDR-SDRAM, IIC, SPI, AXI, Avalon?
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