8. SOC Physical Design Technical Lead

2 weeks ago


Ho Chi Minh City, Ho Chi Minh, Vietnam Faraday Technology Corporation Full time

Responsibilities

  • Participate in ASIC development project with emphasis in place and route implementation (block, subsystem and/or toplevel), timing closure, low power, physical verification, power analysis and IR/EM with package
  • Coordinate and drive physical design activities of the SoC and support crossfunctional engineering effort for signoff closure for tapeout
  • Work closely with frontend, integrating as well as DFT team to optimize performance, power and area
  • Participate in cuttingedge physical design methodology and flow development

Requirements:

  • Must be a power user of Cadence suite (Innovus, QRC, Voltus) or Synopsys suite (ICC2, Fusion Compiler, StarRC, PTSI)
  • Strong in ASIC physical design flow with low power, performance and area optimization techniques
  • Automation and programmingminded, solid coding experience in scripting languages
  • Knowledge of logic design principles, and DFT concepts
  • Successful track records of taping out SoCs in FinFet process is plus
  • BS or MS degree in EE or CS related
  • Good English communication skills
  • At least 5 year working experience


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