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SOC Design Engineer

3 months ago

Ho Chi Minh City, Ho Chi Minh, Vietnam INTEL Full time
As a Physical Design Static Timing Analysis / STA Engineer, your will:

  • Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.
  • Utilize understanding of Design for Test for timing analysis and constraints.
  • Develop and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
  • Work closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
  • Utilize expertise with multivoltage scenarios. Design handling knowledge is expected.
  • Timing closure/convergence execution on Low power designs is an added advantage.
  • Understand LVF/POCV variations and providing feedback to the implementation/methodology teams.

Qualifications:

Minimum Qualifications

  • Bachelor or Master of Science degree in Electrical Engineering or Computer Engineering or related field of study.
  • Have 2 to 10+ years of Static Timing Analysis experience.
  • Excellent communication and project leadership skills.
  • Selfdriven with ability to prioritize work and accomplish tasks quickly with good problemsolving skills.
  • Must be detail oriented with solid written and verbal communication for expressing technical ideas and initiatives.
  • Comfortable task switching and managing multiple tasks at the same time.
Preferred Qualifications

  • Post graduate degree Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study.
  • Demonstrate experience and handson practical knowledge with standardcell based VLSI design methodology and relevant industry standard EDA tools.
  • Experience with Synopsys Primetime or Cadence Tempus.
  • Demonstrate strong analytical and problemsolving skills through relevant experiences with ASIC/SOC design convergence.
  • Demonstrate experience in scripting with Unix shell, Perl and TCL.
  • Good understanding of digital design, circuits, layout with a thorough understanding of CMOS processes.

Inside this Business Group:


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.

From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.

DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.

As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement:


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model:


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.


In certain circumstances the work model may change to accommodate business needs.
JobType

Hybrid