Dft Engineer

**Inside this Business Group**

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative and allows our employees to reach their full potential.
- Define DFT methodology, architecture, and implementation strategies for FPGA SoC which include FPGA core and ASIC like sub-systems and IPs.
- Develop DFT HAS (high-level specification), Scan config file (eg. using Synopsys DC compiler or Fusion compiler), MBIST (eg. Tessent MBIST) insertion file, DFT timing spec, DFT RTL control block, and various DFT scripts and flows.
- Perform pre-silicon Design LINT (static code analyzer)/CDC (clock domain crossing)/RDC (reset domain crossing) check, Spyglass DFT checks, Scan insertion, DFT Timing review, DV (design verification) test plan and waveform review, Scan ATPG, and Scan simulations.
- Bring post-silicon ATPG, MBIST, and IO DFT tests to production. Close collaboration with the Design team to drive for flawless DFT execution. Partner with Product Engineering and Quality Reliability Engineering teams to deliver DFT solutions to meet test cost, test time, yield, and quality goals.

**Qualifications**
- Must have a BS degree in Electrical/Electronic Engineering Computer Science or equivalent with 10 years plus of hands-on experience

**Additional qualifications include**:

- In-depth knowledge of DFT concepts architecture and methodology who has defined the scan architecture for a new product
- In-depth knowledge and hands-on experience in scan insertion who has developed scan scripts from scratch, have experience implementing scan compression, perform ATPG coverage analysis to debug low coverage issues to define solutions to meet coverage goals by using industry-standard tools.
- Strong communications skills and the ability to effectively work with cross-functional teams across geographies are required

**Work Model for this Role**

This role will be eligible for our hybrid work model which

**Inside this Business Group**
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

**Posting Statement**
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**

**Working Model**
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
**In certain circumstances the work model may change to accommodate business needs.