Physical Design Engineer

**The Role**

As part of the Physical Design team at Ampere, you will be responsible for ASIC physical design and implementation on our cutting edge ARMv8 based server on chip solutions that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry. You will have an opportunity to work collaboratively with and learn from industry veteran designers and architects to create a breakthrough design for cloud computing.

Our Physical Design Engineer will work with multi-functional global teams to implement Partition/Block level Constraint development, Synthesis, Floorplan, Place and Route, Timing closure, LEC, IR/EM and DRC/LVS closure for our next generation highly complex 3nm/5nm/7nm/advanced-node Server class Processor products.

**What the Physical Design Team wants you to know**

Being a Physical Design Engineer at Ampere® is interesting, challenging, and will expand your professional breadth. You will learn how a world-class design team develop their microprocessor using Ampere® Arm®-based platform plus our in-house and 3rd party IP portfolio. Also, you will understand pressure of being the leader team in the market, that push us to solve technical problems, and deliver product on time. The experience at Ampere® that you will possess will be valuable for your career path.

**What you will do**
- Responsible for all aspect of physical design from RTL to GDS on sub-micron node, 16nm or lower
- Work with RTL, Architect, package teams to define chip size, chip floorplan, IO location, bumps placement.
- Collaborate with related team (RTL/DV/Power/Implementation) for best PPA (performance, power, area)
- Work with RTL/Implementation team for function ECOs, full chip timing closure, physical design signoff
- Develop physical design methodologies, flow customization/automation, synthesis, LEC, floor-planning, power/clock distribution, IP block assembly, place & route, and timing closure.
- Responsible for enhancing PD flow for more productivity and design efficiency.
- Work with packaging, power-grid designer to plan on bumps, power-grid distribution, power planning, EMIR analysis, for multiple domains at the chip-level.

**What you will bring**
- Min 10+ years of hand-on physical design experience from netlist to GDS on sub-micron node 28nm or lower
- Hand-on experience with Cadence or Synopsys physical implementation tool and Calibre DRC/LVS physical verification tool
- Experience with floorplan trade off, placement and routing approaches, pre
- and post-silicon ECO, timing closure, congestion resolution, IR-drop and crosstalk reduction techniques.
- Experience with high-speed Clock Tree Synthesis, topology and trade off.
- Experience with signal integrity effect and solution
- Experience with constraint debug, timing closure are plus.
- Experience with FinFET technology is a plus.
- Great communication and collaboration skills.
- Excellent analysis, problem solving skills.
- Good English communications skills, both verbal and writing

**Education**
- BS/MS/Ph.D in Electronic/Physic/Computer Engineering/Computer Science or a related field.

**Our Company**

**Our Story**

Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.