5. Sta Engineer

5 months ago


Ho Chi Minh City, Vietnam Faraday Technology Corporation Full time

**Responsibilities**
- Static timing analysis and timing closure (TOP and block)
- Synthesis, low power check, logic equivalence check, clock tree guideline
- Collaborate with DFT teams to create and validate DFT circuit and SDC
- Discuss with customers for data-in qualification & sign-off condition
- Work as project leader/block coordinator to control project schedule and support project members to ensure T/O on-time

**Requirements**:

- Familiar with PrimeTime, Debussy, Verilog-XL, design compiler and formal verification tools
- Excellent team-work and interpersonal skills
- BS or MS degree in EE or CS related
- Good English communication skills
- At least 2 year working experience



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