Digital Ic Design, Staff Engineer

7 months ago

Ho Chi Minh City, Vietnam Marvell Full time

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell is a leading provider of innovative storage technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems.

You will work Storage BU, implementation team.

What You Can Expect
- Responsible for synthesis, formal equivalence check, functional ECO
- Responsible for timing constraints developments, timing closure, timing sign-off of hierarchy blocks and full chip
- Work closely with various multi-functional teams on resolving complex timing issues to ensure successful Tape-out

What We're Looking For
- At least 3+ years’ experience in synthesis and SDC development. Expertise in Synthesis tools (Design Compiler/Genus) and flow
- At least 3+ years’ experience in timing constraints generation and timing closure. Expertise in STA tools (PrimeTime/Tempus/XTOP/Tweaker) and flow
- Hands on experience in Synthesis/SDC constraints development for block level and full chip level
- Hands on experience in Formal Verification (Conformal LEC/Formality)
- Hands on experience in timing/SDC constraints generation and management for block level and full chip level
- Hands on experience in timing closure for complex SoC design
- Hands on experience in Timing ECO & Func ECO
- Knowledge of power estimation & measurement is a plus
- Knowledge of noise and signal integrity effect is a plus
- Knowledge of low power concepts and UPF is a plus
- Knowledge of DFT SDC is a plus
- Experience in PnR is a plus
- Experience in CTS and CTS spec development is a plus
- Proficient in scripting languages (TCL and Perl/Python/Ruby)

LI-UN1

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our

Careers

page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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