Physical Design Engineer/ Sta Engineer
5 months ago
**Mô tả công việc**:
(Mức lương: Thỏa thuận)
- To be responsible for managing technology in projects and providing technical guidance / solutions for work completion.
- To be responsible for providing technical guidance / solutions.
- To develop and guide the team members in enhancing their technical capabilities and increasing productivity.
- To ensure process compliance in the assigned module
and participate in technical discussions/review.
- To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
**Chức vụ**: Nhân Viên/Chuyên Viên
**Hình thức làm việc**: Toàn thời gian
**Quyền lợi được hưởng**:
- 18 paid leaves/year (12 annual leaves and 6 personal leaves)
- Insurance plan based on full salary + 13th month salary + Performance bonus
- Meal allowance of 730,000 VND/month
- 100% full salary and benefits as an official employee from the 1st day of working
- Medical benefit for employee and family
- Working in a fast-paced, flexible, and multinational working environment. Chance to travel onsite (in 53 countries)
- Free snacks, refreshment, and parking
- Internal training (Technical & Functional & English)
- Working time: 8:30 AM - 6:00 PM from Mondays to Fridays
**Yêu cầu bằng cấp (tối thiểu)**: Đại Học
**Yêu cầu công việc**:
MAIN REQUIREMENTS
- Professional experience of executing physical design projects for > 5 years
- Proven ability in technically leading a small/medium size team for executing projects preferred
- Hands on experience on the entire PD Flow from RTL to GDSII
- Should have good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence and Sign-off with in depth expertise in at least one of these domains
- Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters, Isolation cells etc)
- Exposure to static timing analysis fixes including automated ECO generation
- Strong in areas on CTS and skew fixing
- Library preparation in any environment (Synopsys, Cadence etc)
- Working knowledge on Physical verifications tasks at lower nodes (data base merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing ) at block level/chip level
- Job would require complete ownership from netlist/RTL to GDS for blocks at Block level OR full chip level
- Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage
- Working knowledge of scripting language like Perl, TCL will be considered a plus
- Must have the ability to present to senior management, work in a geographically dispersed team and be aware of cross-cultural nuances
- Should be able to define project milestones, identify risks and call out mitigation plans
- Be able to use English in working communication
**Yêu cầu giới tính**: Nam/Nữ
**Ngành nghề**: Cơ Khí,Điện Tử,Điện/Điện tử
Đại Học
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