Memory Layout Design Engineer

2 weeks ago


Ho Chi Minh City, Vietnam Sperton Full time

**Description**
- Cell & block level layout, macro planning, and interconnect
- Physical verification (LVS, DRC, ERC, EMIR)
- Actively participate in layout QA methodology and QA system improvement
- Cooperate with designers for optimal Performance, Power, and Area (PPA)
- Provide mentorship and guidance to junior engineers

**Requirement**
- Familiar with memory layouts such as SRAM, ROM or TCAM
- Familiar with Floor-planning, P/G mesh planning, signal routing, and matching layout
- Familiar with Cadence/Synopsys layout editor and physical verification tools
- Experience in schedule estimation
- BS degree in EE or CS related
- Good English communication skills
- Experience in FinFET is a plus

**Salary**: 20,000,000₫ - 120,000,000₫ per month

Ability to commute/relocate:

- Ho Chi Minh City: Reliably commute or planning to relocate before starting work (required)



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