Staff Engineer
3 weeks ago
I
n your new role you will: D
- efine the v**erification concept for new IP/SoCs B**:
- e in charge of d**eveloping SV-UVM based environments D**:
- evelop and review verification specification D
- **ebug failing tests and analyse the root-cause B**:
- e in charge of m**onitorin g** a**nd r**eporting the verification status P**:
- erform and e**valuate verification regressions a**nd ensure high quality deliveries
Y
ou are best equipped for this task if you have: A
- degree in E**lectrical/Electronic Engineering, Computer Science o**r equivalent M
- inimum 3-5 years of experience within the semiconductor industry K
- nowledge of S**ystem Verilog and UVM verification methodology and complex module test benches E**:
- xperience in using d**igital simulators l**ike Cadence XCelium,knowledge in script languages (Perl, Python, etc.) and d**ata management systems (**Clearcase, GIT, etc.) F
- luent English communication skills
P
**art of your life. Part of tomorrow. I
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