Physical Design Engineer
3 months ago
Negotiable
- Hi-Tech & IT
**RESPONSIBILITIES**:
- Perform Netlist-to-GDS design flow, including floor planning, placement, timing optimization, clock tree synthesis and routing.
- Support STA timing analysis and fixing
- Perform physical verification, including DRC, LVS, IR drop and DFM analysis.
**REQUIREMENTS**:
- Major:EE/CS.
- Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler.
- TOEIC 730~855 is preferred.
- Have experiences in 65/40/28nm IC design experiences will be plus.
**For more information, please contact**:
- Ms. Vo Nguyen Bach Ngan (84) 6291 4188 - Ext: 530
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