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Senior Staff Engineer
2 weeks ago
n your new role you will: B
- e responsible for the v
erification of digital designs ; B
- e able to understand r
equirements & specifications ; F
- ocus on T
est plan and test bench development ; B
- e responsible for I
P verification (Formal, SystemVerilog, UVM) ; S
- upport the F
low & Methodology improvements
Y
ou are best equipped for this task if you have: D
- egree in E
lectronic or Computer Engineering ; M
- in 7 years of industry experience in d
igital verification D:
evelopment of verification environments and methodologies at block and subsystem level ; E
ystemVerilog / Verilog / UVM / VMM ; F
- luency in English.
P
**art of your life. Part of tomorrow. I
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