Design Verification Engineer/ Leader
5 days ago
Experience3+ years ( Leader from 8yoe+ Experience)Work TypeOn siteWork LocationSingaporeSalary (Open to discuss)NegotiableOverviewWe are on the search for Design Verification Engineers to work onsite in Singapore.Description· Collaborate with the design team to understand and define verification requirements forhigh-speed, low power digital circuit designs from definition to implementation.· Own and be involved in all aspects of the functional verification from initial test planning, testcreation and debug. to coverage and sign-off closure.· Own and implement verification of high speed, low power digital designs at IP and System levelusing both coverage driven constraint random and directed testing techniques as well as formalverification.· Own and implement test benches and components such as test and sequence libraries, moni-tors, models and BFMs by applying object oriented programming verification techniques follow-ing UVM methodology.Requirements· 3-7 years of functional verification, advanced knowledge of ASIC/SOC Design flow and state ofthe art verification flow.. Proficient with Verilog, System Verilog and UVM.· Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processesand flows.· Good at working in Linux and Windows environments.· Strong analytical and problem-solving skills with pronounced attention to detail.· Automating workflows in a distributed compute environment.· Capable of independently driving tasks and activities to completion in an organized and timelymanner with excellent quality.. Good skills of English communication.ADVANTAGES:· RTL design knowledge/experience is a plus pointACADEMIC CREDENTIALS:. Major in EE, CS or related.Interview ProcessTechnical assessment from BitSilica -> Interview with client
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