Serdes Design Verification
2 days ago
International company
- Full flow IC Design
- New project in Vietnam
**EXPERT DESIGN VERIFICATION ENGINEER**
**(Senior Engineer)**
Our team is performing design and verification for Serdes IP (High speed interface) as the below steps:
- Make DRBFM, target specification, implementation specification.
- Generate/coding full or a part of IP.
- Perform UT, CT & Palladium verification.
- Perform synthesis and checkers (HLDRC, DFTcheck, STAcheck).
- Perform test point insertion, Meta-FF and TMR.
- Release module SDC and perform STA timing check.
**Requirement**:
[UCIe] 1 position
1. Knowledge of UCIe/CXL/PCIe6/CXS.B/AXI
Eough Experience of specification development
Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
Enough Experience of Synthesis, STA, SDC, DFT
Enough Experience of Synopsys IP handling
2. (if hiring 1 is not possible)
Experience of specification development
Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
Enough Experience of Synthesis, STA, SDC, DFT
Enough Experience of Synopsys IP handling
[DP] 1 position
1. Knowledge of DP/HDCP/DSC
Enough Experience of specification development
Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
Enough Experience of Synthesis, STA, SDC, DFT
Enough Experience of Synopsys IP handling
2. (if hiring 1 is not possible)
Experience of specification development
Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
Enough Experience of Synthesis, STA, SDC, DFT
Enough Experience of Synopsys IP handling
[PCIe6/PCIe4/USB3.x/USB2/UFS/CSI/DSI] 4 positions
Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
Enough Experience of Synthesis, STA, SDC, DFT
Communication skills with relevant departments or IP vender
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