Asic Engineer
1 week ago
**Description**
- Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers
- Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG, and ATPG generation
- Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
**Requirement**
- BS or MS degree in EE or CS-related, 5+ years of work experience
- Experience in advanced node process is a plus
- Experienced in the chip design flow and chip implementation flow
- Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools
- Familiar with DFT-related flow and utilities is a plus
- Fluent in English
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