Physical Design Engineer
1 week ago
**Description**
- Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes include floor planning, power plan synthesis, and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
- Responsible for physical verification including DRC, LVS, and ESD checking
**Requirement**
- BS or MS degree in EE or CS-related, 3+ years of work experience
- Experience in advanced node process is a plus
- Experienced in Cadence Innovus flow or Synopsys ICC2 flow
- Experienced in hierarchical implementation, timing closure, IR drop analysis, and crosstalk analysis is a plus
- Experienced in physical verification and layout editing is a plus
- Fluent in English (Chinese is a plus)
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