[urgent] Layout Engineer

1 week ago


Hanoi, Vietnam Navigos Search Full time

**Mô tả công việc**:
(Mức lương: Thỏa thuận)
- As an ASIC layout designer, you will be responsible for analog layout design from block level, up

to top level IC integration and physical verification for advanced ASIC in MEMS sensor.
- You will work with international design team to ensure the layout delivery on time and in quality,

then execute whole tape-out flow together with wafer foundry
**Chức vụ**: Nhân viên/Chuyên viên

**Hình thức làm việc**: Toàn thời gian

**Quyền lợi được hưởng**:
13th payment + KPI Bonus
**Yêu cầu bằng cấp (tối thiểu)**: Đại Học

**Yêu cầu công việc**:

- Bachelor/master's degree majored in microelectronics or relevant electrical engineering field (main course: analog circuits, digital circuits, semiconductor device and physics, semiconductor

manufacturing).
- Experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge

pump, bandgap design
- In-depth knowledge of Samsung 65nm 28nm BCD SOI technologies and design rules
- Solid knowledge of industry standard IC layout conventions and rules for reducing layout risk
- Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification

and extraction tools Calibre, PVS, Assura, Knowing Laker tool is an advantage.
- Understanding of CMOS process side effect and known how to minimize the risk in layout

(e.g. lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc...)
- Be able to analysis EM and IR drop
- Skilled in Linux operating system
- Strong problem-solving skills
- Fluent English in writing and reading
- Experience in leading a full chip layout from floorplan to tape-out
- Auto place and route experience for non-timing critical design is a plus

**Yêu cầu giới tính**: Nam/Nữ

**Ngành nghề**: Cơ Điện,Điện/Điện tử

Đại Học
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