Senior Analog Layout Engineer in Hanoi/ Ho Chi Minh

2 months ago

Hà Nội, Vietnam Synopsys Full time

**Introduction**
- At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
- Our Analog Mixed Signal IP Team is seeking for Analog Mixed Signal (A&MS) Layout Engineer to join our talented team.
- If you are an experienced A&MS Layout Engineer who wants to join a team of experts in high-end Analog Mixed Signal design with latest process technologies and a great team player, this can be a perfect position for you.

**Opportunities**
- SNPS is the world number one IP provider. Work with many experts from around the world and talented highly motivated Viet Nam engineering team
- Professional, innovative, fair and fun working environment. Strong culture company.
- Competitive salary and benefit. Strong support from company for health: Insurance, Sport clubs: Football, Ping-Pong, Badminton, Yoga, Zumba
- Strong support from company for team building, social activities: Team trip, Family Day
- Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
- Clear career path of self-development to either Technical Expert or Design Leader/Manager
- Travel to USA, Europe and Asia for training or on-site support.

**Authority**
- Schedule and manage work flow, tasks, design data/documentations.
- Normally receives little instruction on day-to-day work, general instructions on new assignments.
- Demonstrates good judgment in selecting methods and techniques for obtaining solutions.

**Job Descriptions**
- Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
- Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
- Participate in building and enhancing layout flow for faster, higher quality design process.
- Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
- Do PERC verification for ESD/LUP checks
- Complete all design quality checks and data quality checks
- Work with Place and Route engineer to integrate analog layouts into top level.
- Work with Package team to ensure the integration of top die and package
- Do design reviews across global team
- May collaborate in package design (interposer design, RDL design)
- Work closely with design team in Viet Nam, USA, Canada and other countries to ensure the success of the whole product.
- May join research programs to implement new ideas for future products and flows
- May lead a layout team to complete a full design block
- Mentor junior layout engineers or interns

**Skills Requirements**:

- BS in Electronics Engineering, Electromechanics, Telecommunications.
- 3+ years of experience in custom layout.
- Familiar with Layout entry tools: Cadence, Synopsys
- Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
- Understand basic semiconductor fabrication processes
- Understand MOSFET fundamentals
- Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
- Experienced with mentoring/leading junior layouts to complete a design.
- Experienced with writing layout review presentations and layout verification reports
- Good English communication
- Strong team player
- Self-motivated, humble, honest and willing to learn.

**_
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability._

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