Senior Top-level Analog Layout Design Engineer
1 month ago
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. And our Analog Mixed Signal IP Team is seeking for Senior Analog Layout Design Engineer to join our talented team.
If you are an experienced A&MS Layout Engineer who wants to join a team of experts in high-end Analog Mixed Signal design with latest process technologies and a great team player, this can be a perfect position for you.
**Responsibilities**:
- Work on custom layout for high-level layout of Analog IPs which are required best routing for power and signal integrity...
- Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout routing
- Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
- Do PERC verification for ESD/LUP checks
- Complete all design quality checks and data quality checks
- Schedule and manage workflow, tasks, design data/documentations
- Work with Place and Route engineer to integrate analog layouts into top level
- Work with Package team to ensure the integration of top die and package
- Work with Circuit team to optimize performance on Power and Signal integrity
- Work closely with design team in Viet Nam, USA, Canada and other countries to ensure the success of the whole product.
- Do design reviews across global team
- Participate in building and enhancing layout flow for faster, higher quality design process.
- Demonstrates good judgment in selecting methods and techniques for obtaining solutions.
- May join research programs to implement new ideas for future products and flows
- Normally receives little instruction on day-to-day work, general instructions on new assignments.
- May manage a small layout team to complete a full design block
- Mentor junior layout engineers or interns
**Requirements**:
- Bachelor's or Master's degree or above, major in Electrical, Electronic and Telecommunication Engineering, Computer Science, Automation and Control, Mechatronic Engineering or any other relevant.
- From 2 years of experience in custom layout.
- Familiar with Layout entry tools: Cadence, Synopsys
- Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
- Understand basic semiconductor fabrication processes
- Understand MOSFET fundamentals
- Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
- Experienced with mentoring/leading junior layouts to complete a design.
- Experienced with writing layout review presentations and layout verification reports
- Good at English communication
- Dedicated team player, Self-motivated, humble, honest and willing to learn.
**Opportunities**
- SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented highly motivated Viet Nam engineering team
- Professional, innovative, fair and fun working environment. Exceptional culture company.
- Competitive salary and benefit. Excellent support from company for health: Insurance, Sport clubs: Football, Table tennis, Badminton, Yoga, Zumba
- Solid support from the company for team building, social activities: Team trip, Family Day
- Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
- Clear career path of self-development to either Technical Experts or Design Management
- Travel to USA, Europe and Asia for training or on-site support.
Synopsys delivers leading silicon to systems design solutions that maximize our customers’ R&D capability and productivity. Companies trust Synopsys to pioneer new technologies getting them to market faster without compromise.
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