Design Implementation Engineer

2 weeks ago


Ho Chi Minh City, Vietnam Ampere Computing Full time

**The Role**

In this role, you will be responsible for ASIC implementation, including synthesis, floorplanning, place and route, timing closure, on our cutting edge ARMv8 based server on chip solutions (X-Gene) that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology (5nm and 7nm) nodes available in the industry.

**What the Team wants you to know**

You should be a motivated person and a team player who is ready to work in a startup like culture. Our mantra is “Ampere First” and as part of the team you should be thinking about how I can contribute to make a better Server product.

**What you will do**
- Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off
- Run physical synthesis on large and medium size blocks
- Implement and verify other aspects netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc
- Develop mid-end to back end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc
- Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners
- Perform timing closure across all corners to ensure successful tapeout following our aggressive deadlines
- Generate and implement functional ECO
- Run Logic Equivalent Check (LEC) from RTL to prelayout/postlayout netlist

**What you will bring**
- Minimum 1+ years of development mid-end to back-end implementation flows
- Experience with Verilog or HDL languages and tools is a plus
- Experience in scripting languages (PERL, TCL, shell, etc.)
- Experience in ASIC methodologies and tools like Genus, Cadence Innovus, Synopsys Primetime, Cadence Tempus, LEC, CDC, etc.
- Physical design experience a plus
- Synthesis, place and route and Timing analysis experience
- Good English and Vietnamese communications skills, both speaking and writing

**Education**
- BS/MS/Ph.D. in Electronic Engineering/Computer Engineering or equivalent



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