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Verification Engineer
1 week ago
_Job Description:
_
Verification Planning:
- Develop detailed verification plans aligned with design specifications.
- Define functional coverage goals and metrics to track progress.
- Collaborate with design teams to understand the architecture and intended functionality.
Testbench Development:
- Build comprehensive testbenches using SystemVerilog and UVM (or applicable methodologies).
- Develop selfchecking test cases, including directed and constrainedrandom tests.
- Integrate assertions for effective design monitoring.
Simulation and Debugging:
- Execute simulations using industrystandard simulators (Cadence, Synopsys, Mentor Graphics, etc.).
- Analyze waveforms, debug design failures, and work closely with designers to isolate and resolve issues.
- Optimize simulations for performance and efficiency.
Documentation and Process Improvement:
- Maintain meticulous documentation of test plans, environments, and results.
- Contribute to the refinement of verification methodologies and best practices.
- Qualiifications_
Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Experience:
- 2+ years of experience in RTL verification of digital designs.
- Solid understanding of ASIC or FPGA design flows.
Skills:
- Expertise in SystemVerilog (or VHDL) and objectoriented programming concepts.
- Indepth knowledge of UVM or other verification methodologies.
- Experience with coveragedriven verification techniques.
- Strong debugging and analytical skills.
- Scripting abilities (Perl, Python, TCL, etc.)
- Excellent teamwork and communication skills
- Welfare & benefits_
- Competitive salary.
- Opportunity to participate in major projects on Netflix, Apple TV, Disney, etc.
- Enjoy full insurance benefits and comply with labor laws.
- Free lunch, drinks, and snacks at the office.
- Receive professional training and guidance to improve expertise.
Work address:
Dreamplex Building, 195 Dien Bien Phu, Ward 15, Binh Thanh, Ho Chi Minh City.
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